A variety of transmission lines are used for transmission lines in microwave bands and millimeter-wave bands. Examples of the transmission lines include a grounded coplanar transmission line including a dielectric plate having a ground electrode on the substantially entire first surface thereof and a coplanar on the second surface thereof, a grounded slot transmission line including a dielectric plate having a ground electrode on the first surface thereof and a slot on the second surface thereof, and a planar dielectric transmission line (PDTL) including a dielectric plate having opposing slots on either surface thereof.
These transmission lines have a structure including two parallel planar conductors. Accordingly, for example, if an electromagnetic field is disturbed at input and output portions or a bent portion of the transmission line, a spurious mode wave, such as a so-called parallel plate mode wave, is induced between the two parallel planar conductors. The spurious mode wave (hereinafter simply referred to as an “unwanted wave”) disadvantageously propagate between the two parallel planar conductors. If unwanted waves propagate (leak), the unwanted waves interfere with each other between neighboring transmission lines, and therefore, a problem of signal leakage occurs. In addition, since partial energy of the propagation waves leaks in the form of unwanted waves, the partial energy is not reconstructed as transmitted waves. Consequently, transmission loss occurs.
Non-patent document 1 and Patent document 1 describe transmission lines in which a unit cell pattern including a capacitive region and an inductive region is repeatedly arranged in two-dimensional directions (longitudinal and transverse directions) to prevent such propagation of unwanted waves.
FIG. 1(A) illustrates the pattern of a unit cell formed on a substrate described in Non-Patent Document 1. FIG. 1(B) illustrates an example of a band gap caused by a planar circuit described in Non-Patent Document 1. In the planar circuit according to Non-Patent Document 1, the unit cell illustrated in FIG. 1(A) is arranged on an upper surface of the substrate in two-dimensional directions. A ground electrode is formed on the entire lower surface. Let Γ be the center of the unit cell, X be an end of the unit cell extending from Γ in an X-axis direction, and M be an end of the unit cell extending from X in a Y direction. Then, FIG. 1(B) illustrates the frequencies in each of the modes of the wave number space in a path Γ-X-M-Γ. In this example, a unit cell having sides of about 3 mm is arranged on a surface of a dielectric substrate having a relative permittivity of 10.2 and a thickness of about 0.6 mm. A band gap (a forbidden band or stopband) between about 11 GHz and about 14 GHz appears between a first mode f1 and a second mode f2. A band gap between about 18 GHz and about 22 GHz appears between the second mode f2 and a third mode f3.
A reduced-width crisscross strip portion of the unit cell serves as an inductive region (an inductance component). The combined pattern of rectangular patterns formed at the center and four corners of the unit cell serves as a capacitive region (a capacitance component).
However, to design a planar circuit having such a unit cell in order to obtain a band gap frequency of 10 GHz, the planar circuit needs to have a unit cell having sides as long as about 3 mm. Thus, to lay out the planar circuit together with an interconnection pattern of the circuit, the design flexibility (layout flexibility) is decreased.
In contrast, the layout flexibility of the planar circuit described in Patent Document 1 is increased by decreasing the size of the unit cell. In addition, the loss characteristic does not deteriorate. FIG. 2 illustrates an example of a unit cell described in Patent Document 1. In the planar circuit, a capacitive region C is disposed at the center of the unit cell. An inductive region L having a meandering line shape is disposed around the capacitive region C. In this way, by forming a unit cell having a large capacitance component of the capacitance region C and a large inductance component of the inductive region L, the size of the unit cell can be decreased.
Patent document 2 describes a planar circuit that prevents the propagation of a spurious mode using a conductor transmission line and a plurality of filters connected to the conductor transmission line. FIG. 3 illustrates an example of the planar circuit described in Patent Document 2. The planar circuit includes two parallel conductor transmission lines 7A and 7B. Two spiral transmission lines 8A and 8B extend parallel to each other from the base portion of a resonator disposed in each of the stages. The top ends 8C of the two spiral transmission lines 8A and 8B are connected. The base portions of the resonators are connected to a plurality of portions of the transmission line 7A, which is one of the two parallel conductor transmission lines 7A and 7B.
Non-patent Document 1: T. Itoh, et. al. “Aperture-Coupled Patch Antenna on UC-PBGSubstrate,” IEEE Trans. Vol. 47, no. 11, pp. 2123-2130, November 1999.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 2000-101301
Patent Document 2: Japanese Unexamined Patent Application Publication No. 2003-258504
However, in the planar circuit including the conductive region of the unit cell having a meandering line shape disclosed in Patent Document 1, the band gap is disadvantageously decreased in a bottleneck shape in accordance with the direction of waves propagating in the substrate as described later.
As shown in FIG. 3, in the planar circuit described in Patent Document 2, filters, each including the conductor transmission lines 7A and 7B and a resonator 8, are basically one-dimensionally disposed. In the structure in which the filters, each including the conductor transmission lines 7A and 7B and the resonator 8, are one-dimensionally disposed, the geometric asymmetry (anisotropic nature) results in differences in the electrical characteristics in accordance with the propagation direction. In addition, since an interconnection line is connected at an angle of 45° for a direct current when a direct current bias voltage is applied, it is difficult to design the planar circuit.